JCSE, vol. 20, no. 2, pp.78-88, 2026

DOI: http://dx.doi.org/10.5626/JCSE.2026.20.2.78

Recent Research Activities in Design Technology Co-optimization of Electronic Design Automation for Multi-bit Flip-flop Banks

Taewhan Kim
School of Electrical and Computer Engineering, Seoul National University, Seoul, Korea

Abstract: This paper surveys a number of noticeable recent research activities on the design and technology co-optimization (DTCO) with multi-bit flip-flop (MBFF) cells, each of which is a collection of multiple flip-flops (i.e., small bank components) sharing internal clocking logic, in design automation perspective. MBFF cells are widely used for low-power design, but they incur a number of critical limitations which should be overcome in the context of DTCO where its objective is to set the cell architecture parameters that leads to an optimal performance/power/area (PPA) of target design implementation using the cells. The limitations are, due to the grouping of individual flip-flops, i.e., very large size as well as the sharing of internal clock inverters, the layout space waste in MBFF cells, the inflexibility in optimizing interconnects, and the inflexibility in optimizing timing. Specifically, the DTCO research activities surveyed in this paper are the utilization of the diverse structures of MBFF cells in optimizing interconnect; the utilization of the empty space in MBFF cells in optimizing timing; the exploitation of debanking the MBFF cell instances to trade off power against timing; and the exploitation of hybrid-VT (threshold voltage) MBFF cells for fine-grained trade-off between cell delay and leakage power.

Keyword: EDA; Electronic design automation; Hardware optimization; Storage element; Flip-flop cells; Lowpower design; Physical implementation

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