JCSE, vol. 6, no. 4, pp.267-278, 2012

DOI: http://dx.doi.org/10.5626/JCSE.2012.6.4.267

Static Timing Analysis of Shared Caches for Multicore Processors

Wei Zhang, Jun Yan
Department of Electrical and Computer Engineering, Virginia Commonwealth University Richmond, VA, USA/ MathWorks Inc., Boston, MA, USA

Abstract: The state-of-the-art techniques in multicore timing analysis are limited to analyze multicores with shared instruction caches only. This paper proposes a uniform framework to analyze the worst-case performance for both shared instruction caches and data caches in a multicore platform. Our approach is based on a new concept called address flow graph, which can be used to model both instruction and data accesses for timing analysis. Our experiments, as a proof-of-concept study, indicate that the proposed approach can accurately compute the worst-case performance for real-time threads running on a dual-core processor with a shared L2 cache (either to store instructions or data).

Keyword: Performance; Reliability; WCET analysis; Multicore processors; Unified caches

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