JCSE, vol. 7, no. 1, pp.67-80, 2013

DOI: http://dx.doi.org/10.5626/JCSE.2013.7.1.67

Multicore Real-Time Scheduling to Reduce Inter-Thread Cache Interferences

Yiqiang Ding, Wei Zhang
Department of Electrical and Computer Engineering, Virginia Commonwealth University, Richmond, VA 23284, USA

Abstract: The worst-case execution time (WCET) of each real-time task in multicore processors with shared caches can be significantly affected by inter-thread cache interferences. The worst-case inter-thread cache interferences are dependent on how tasks are scheduled to run on different cores. Therefore, there is a circular dependence between real-time task scheduling, the worst-case inter-thread cache interferences, and WCET in multicore processors, which is not the case for single-core processors. To address this challenging problem, we present an offline real-time scheduling approach for multicore processors by considering the worst-case inter-thread interferences on shared L2 caches. Our scheduling approach uses a greedy heuristic to generate safe schedules while minimizing the worst-case inter-thread shared L2 cache interferences and WCET. The experimental results demonstrate that the proposed approach can reduce the utilization of the resulting schedule by about 12% on average compared to the cyclic multicore scheduling approaches in our theoretical model. Our evaluation indicates that the enhanced scheduling approach is more likely to generate feasible and safe schedules with stricter timing constraints in multicore real-time systems.

Keyword: Performance; Reliability; Real-time scheduling; WCET; Multicore processor

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