JCSE, vol. 12, no. 1, pp.24-35, 2018

DOI: http://dx.doi.org/10.5626/JCSE.2018.12.1.24

Toward Optimal FPGA Implementation of Deep Convolutional Neural Networks for Handwritten Hangul Character Recognition

Hanwool Park, Yechan Yoo, Yoonjin Park, Changdae Lee, Hakkyung Lee, Injung Kim, and Kang Yi
School of Computer Science and Electrical Engineering, Handong Global University, Pohang, Korea

Abstract: Deep convolutional neural network (DCNN) is an advanced technology in image recognition. Because of extreme computing resource requirements, DCNN implementation with software alone cannot achieve real-time requirement. Therefore, the need to implement DCNN accelerator hardware is increasing. In this paper, we present a field programmable gate array (FPGA)-based hardware accelerator design of DCNN targeting handwritten Hangul character recognition application. Also, we present design optimization techniques in SDAccel environments for searching the optimal FPGA design space. The techniques we used include memory access optimization and computing unit parallelism, and data conversion. We achieved about 11.19 ms recognition time per character with Xilinx FPGA accelerator. Our design optimization was performed with Xilinx HLS and SDAccel environment targeting Kintex XCKU115 FPGA from Xilinx. Our design outperforms CPU in terms of energy efficiency (the number of samples per unit energy) by 5.88 times, and GPGPU in terms of energy efficiency by 5 times. We expect the research results will be an alternative to GPGPU solution for real-time applications, especially in data centers or server farms where energy consumption is a critical problem.

Keyword: Deep convolutional neural networks; Deep learning accelerator; FPGA optimal design; Hangul character recognition

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