JCSE, vol. 5, no. 1, pp.1-18, 2011

DOI: 10.5626/JCSE.2011.5.1.001/

Bounding Worst-Case Performance for Multi-Core Processors with Shared L2 Instruction Caches

Jun Yan, Wei Zhang
Mathworks, Boston, MA, USA Department of Electrical and Computer Engineering Virginia Commonwealth University Richmond, VA, USA

Abstract: As the first step toward real-time multi-core computing, this paper presents a novel approach to bounding the worst-case performance for threads running on multi-core processors with shared L2 instruction caches. The idea of our approach is to compute the worst-case instruction access interferences between different threads based on the program control flow information of each thread, which can be statically analyzed. Our experiments indicate that the proposed approach can reasonably estimate the worst-case shared L2 instruction cache misses by considering the inter-thread instruction conflicts. Also, the worst-case execution time (WCET) of applications running on multi-core processors estimated by our approach is much better than the estimation by simply assuming all L2 instruction accesses are misses.

Keyword: Real-time and embedded systems, Performance, Reliability, Worst-case Execution Time Analysis, Multicore Processors, Shared Caches, Hard Real-timeyday loans onlin

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