JCSE, vol. 12, no. 4, pp.139-148, December, 2018

DOI: http://dx.doi.org/10.5626/JCSE.2018.12.4.139

Estimating the Worst-Case Execution Time of the Shared Data Cache in Integrated CPU-GPU Architectures

Yijie Huangfu and Wei Zhang
Department of Electrical and Computer Engineering, Virginia Commonwealth University, Richmond, VA, USA

Abstract: Integrated CPU-GPU architectures have the potential to increase performance and energy efficiency for a variety of applications, due to their tight coupling of the CPU and GPU cores. However, in order to serve hard real-time and safety critical applications, the integrated CPU-GPU architecture must be time-predictable and worst-case execution time (WCET) analyzable. In this work, we study the shared data last-level cache (LLC) in the integrated CPU-GPU architecture and propose an access interval-based method in order to estimate the worst-case cache misses of the LLC. The results indicate that the proposed technique can effectively improve the accuracy of the miss rate estimation in the LLC. We also find that the improved LLC miss rate estimations can be used to further improve the WCET estimations of the GPU kernels running on the integrated CPU-GPU architecture.

Keyword: Graphics Processing Units (GPUs); Worst-Case Execution Time (WCET); Cache memories; Integrated CPU-GPU

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