JCSE, vol. 8, no. 4, pp.215-227, December, 2014

DOI: http://dx.doi.org/10.5626/JCSE.2014.8.4.215

Two-Level Scratchpad Memory Architectures to Achieve Time Predictability and High Performance

Yu Liu and Wei Zhang
Department of Electrical and Computer Engineering, Virginia Commonwealth University, Richmond, VA, USA

Abstract: In modern computer architectures, caches are widely used to shorten the gap between processor speed and memory access time. However, caches are time-unpredictable, and thus can significantly increase the complexity of worst-case execution time (WCET) analysis, which is crucial for real-time systems. This paper proposes a time-predictable twolevel scratchpad-based architecture and an ILP-based static memory objects assignment algorithm to support real-time computing. Moreover, to exploit the load/store latencies that are known statically in this architecture, we study a Scratchpad Sensitive Scheduling method to further improve the performance. Our experimental results indicate that the performance and energy consumption of the two-level scratchpad-based architecture are superior to the similar cache based architecture for most of the benchmarks we studied.

Keyword: Hard real-time systems; Scratch-pad memory; Time predictability

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